The present disclosure relates to semiconductor devices, and more particularly to electrical contacts to the gate structures of semiconductor devices.
Current complementary metal oxide semiconductor (CMOS) technology uses silicides as contacts to source/drain (S/D) regions and gate structures of the n-type and p-type semiconductor devices. In order to be able to make integrated circuits (ICs), such as CMOS devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties. However, with increased scaling, the etch processes that are typically used in forming the semiconductor devices may not have the controllability that is required for manufacturing.